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19-5036; Rev 5; 1/11
KIT ATION EVALU ABLE AVAIL
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
General Description Features
o 16-Bit ADC (MAX11044/MAX11045/MAX11046) and 14-Bit ADC (MAX11054/MAX11055/MAX11056) 8-Channel ADC (MAX11046/MAX11056) 6-Channel ADC (MAX11045/MAX11055) 4-Channel ADC (MAX11044/MAX11054) o Single Analog and Digital Supply o High-Impedance Inputs Up to 1G o On-Chip T/H Circuit for Each Channel o Fast 3s Conversion Time o High Throughput: 250ksps for Each Channel o 16-Bit/14-Bit, High-Speed, Parallel Interface o Internal Clocked Conversions o 10ns Aperture Delay o 100ps Channel-to-Channel T/H Matching o Low Drift, Accurate 4.096V Internal Reference Providing an Input Range of 5V o External Reference Range of 3.0V to 4.25V, Allowing Full-Scale Input Ranges of 4.0V to 5.2V o 56-Pin (8mm x 8mm) TQFN and 64-Pin (10mm x 10mm) TQFP Packages o Evaluation Kit Available
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
The MAX11044/MAX11045/MAX11046 16-bit and MAX11054/MAX11055/MAX11056 14-bit ADCs offer 4, 6, or 8 independent input channels. Featuring independent track and hold (T/H) and SAR circuitry, these parts provide simultaneous sampling at 250ksps for each channel. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 accept a 5V input. All inputs are overrange protected with internal 20mA input clamps providing overrange protection with a simple external resistor. Other features include a 4MHz T/H input bandwidth, internal clock, and internal or external reference. A 20MHz, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 operate with a 4.75V to 5.25V analog supply and a separate flexible 2.7V to 5.25V digital supply for interfacing with the host without a level shifter. The MAX11044/MAX11045/MAX11046 are available in a 56-pin TQFN and 64-pin TQFP packages while the MAX11054/MAX11055/MAX11056 are available in TQFP only and operate over the extended -40C to +85C temperature range.
Applications
Automatic Test Equipment Power-Factor Monitoring and Correction Power-Grid Protection Multiphase Motor Control Vibration and Waveform Analysis
Functional Diagram
AVDD DVDD DB15**
Ordering Information
PART MAX11044ETN+ MAX11044ECB+ MAX11045ETN+ MAX11045ECB+ MAX11046ETN+ MAX11046ECB+ MAX11054ECB+ MAX11055ECB+ MAX11056ECB+ PIN-PACKAGE 56 TQFN-EP* 64 TQFP-EP* 56 TQFN-EP* 64 TQFP-EP* 56 TQFN-EP* 64 TQFP-EP* 64 TQFP-EP* 64 TQFP-EP* 64 TQFP-EP* CHANNELS 4 4 6 6 8 8 4 6 8
BIDIRECTIONAL DRIVERS
CLAMP
S/H
16-/14-BIT ADC
8 x 16-/14-BIT REGISTERS
CH0
DB4 DB3/CR3 DB0/CR0
CH7
CLAMP
S/H
16-/14-BIT ADC
AGNDS
CONFIGURATION REGISTERS INTERFACE AND CONTROL MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 10k INT REF REF BUF EXT REF
WR RD CS CONVST SHDN EOC DGND RDC RDC_SENSE*
AGND
BANDGAP REFERENCE REFIO
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configurations appear at end of data sheet.
*CONNECTED INTERNALLY TO RDC ON THE TQFN PARTS
**MAX11044/MAX11045/MAX11046 MAX11046/MAX11056
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND and DGND .....................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AGNDS to AGND...................................................-0.3V to +0.3V CH0-CH7 to AGND ...............................................-7.5V to +7.5V REFIO, RDC to AGND ..................................-0.3V to the lower of (VAVDD + 0.3V) and +6V EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of (VDVDD + 0.3V) and +6V DB0-DB15 to AGND ....................................-0.3V to the lower of (VDVDD + 0.3V) and +6V Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................50mA Continuous Power Dissipation 56-Pin TQFN (derate 47.6mW/C above +70C) ....3809.5mW 64-Pin TQFP (derate 43.5mW/C above +70C)........3478mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +4.75V to +5.25V, VDVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F, CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity No Missing Codes Offset Error Channel Offset Matching Offset Temperature Coefficient Gain Error Positive Full-Scale Error Negative Full-Scale Error Positive Full-Scale Error Matching Negative Full-Scale Error Matching Channel Gain-Error Matching Gain Temperature Coefficient DYNAMIC PERFORMANCE MAX11044/MAX11045/ MAX11046 fIN = 10kHz, full-scale input MAX11054/MAX11055/ MAX11056 MAX11044/MAX11045/ MAX11046 fIN = 10kHz, full-scale input MAX11054/MAX11055/ MAX11056 91 84.5 90.5 84.5 92.3 dB 85.2 92 dB 85.2 Between all channels 0.5 N INL DNL MAX11044/MAX11045/MAX11046 MAX11054/MAX11055/MAX11056 MAX11044/MAX11045/MAX11046 MAX11054/MAX11055/MAX11056 MAX11044/MAX11045/MAX11046 MAX11054/MAX11055/MAX11056 MAX11044/MAX11045/MAX11046 MAX11054/MAX11055/MAX11056 16 14 > -2 -0.8 > -1 -0.6 16 14 Bits 0.4 0.13 0.4 0.15 < +2 +0.8 < +1.2 +0.6 LSB LSB Bits 0.001 0.001 0.8 0.015 0.015 0.015 0.01 0.01 0.01 0.015 0.015 %FSR %FSR V/C %FSR %FSR %FSR %FSR %FSR %FSR ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
Signal-to-Noise Ratio
SNR
Signal-to-Noise and Distortion Ratio
SINAD
2
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F, CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MAX11044/MAX11045/ MAX11046 fIN = 10kHz, full-scale input MAX11054/MAX11055/ MAX11056 MAX11044/MAX11045/ MAX11046 fIN = 10kHz, full-scale input MAX11054/MAX11055/ MAX11056 fIN = 60Hz, full scale and ground on adjacent channel (Note 2) MIN 98 95 TYP 104 dB 104 -105 -104 -98 dB -95 MAX UNITS
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Spurious-Free Dynamic Range
SFDR
Total Harmonic Distortion
THD
Channel-to-Channel Crosstalk ANALOG INPUTS (CH0-CH7) Input Voltage Range Input Leakage Current Input Capacitance Input-Clamp Protection Current TRACK AND HOLD Throughput Rate Acquisition Time Full-Power Bandwidth Aperture Delay Aperture-Delay Matching Aperture Jitter INTERNAL REFERENCE REFIO Voltage REFIO Temperature Coefficient EXTERNAL REFERENCE Input Current REF Voltage-Input Range REF Input Capacitance VREF VREF tACQ
-126
-100
dB
(Note 3) -1 15 Each input simultaneously Per channel -3dB point -0.1dB point -20 1 1 4 > 0.2 10 100 50 4.08 4.096 5 -10 3.00 15 VIH VIL CIN IIN VIN = 0V or VDVDD VDVDD = 2.7V to 5.25V VDVDD = 2.7V to 5.25V 10 2
1.22 x VREFIO +1 +20 250 1000
V A pF mA ksps s MHz ns ps psRMS
4.112
V ppm/C
+10 4.25
A V pF V
DIGITAL INPUTS (CR0-CR3, RD, WR, CS, CONVST) Input Voltage High Input Voltage Low Input Capacitance Input Current 0.8 10 V pF A
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F, CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN VDVDD 0.4 0.25 15 4.75 2.70 MAX11046/MAX11056, VAVDD = 5V MAX11045/MAX11055, VAVDD = 5V MAX11044/MAX11054, VAVDD = 5V MAX11046/MAX11056, VDVDD = 3.3V Digital Supply Current (Note 9) IDVDD IDVDD IAVDD VAVDD = 4.9V to 5.1V (Note 5) MAX11044/MAX11045/ MAX11046 MAX11054/MAX11055/ MAX11056 1 LSB 0.25 MAX11045/MAX11055, VDVDD = 3.3V MAX11044/MAX11054, VDVDD = 3.3V Shutdown Current 5.25 5.25 48 39 30 7.0 6.5 5.5 10 10 A mA mA 0.4 10 TYP MAX UNITS DIGITAL OUTPUTS (DB0-DB15, EOC) Output Voltage High Output Voltage Low Three-State Leakage Current Three-State Output Capacitance Analog Supply Voltage Digital Supply Voltage Analog Supply Current AVDD DVDD IAVDD VOH VOL ISOURCE = 1.2mA ISINK = 1mA DB0-DB15, VRD VIH or VCS VIH DB0-DB15, VRD VIH or VCS VIH V V A pF V V
Power-Supply Rejection
PSR
TIMING CHARACTERISTICS (Note 4) CONVST Rise to EOC Acquisition Time CS Rise to CONVST Rise CONVST Rise to EOC Rise EOC Fall to CONVST Fall CONVST Low Time CS Fall to WR Fall WR Low Time CS Rise to WR Rise Input Data Setup Time Input Data Hold Time CS Fall to RD Fall RD Low Time tCON tACQ tQ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 CONVST mode B0 = 0 only (Note 7) CONVST mode B0 = 1 only 0 20 0 20 0 10 1 0 30 Sample quiet time (Note 6) Conversion time (Note 6) 1 500 47 140 3 1000 s s ns ns ns ns ns ns ns ns ns ns ns
4
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +2.70V to +5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F, CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted, fSAMPLE = 250ksps. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER RD Rise to CS Rise RD High Time RD Fall to Data Valid RD Rise to Data Hold Time SYMBOL t10 t11 t12 t13 (Note 7) 5 CONDITIONS MIN 0 10 35 TYP MAX UNITS ns ns ns ns
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
See the Definitions section at the end of the data sheet. Tested with alternating channels modulated at full scale and ground. See the Input Range and Protection section for more details. CLOAD = 30pF on DB0-DB15 and EOC. Inputs (CH0-CH7) alternate between full scale and zero scale. fCONV = 250ksps. All data is read out. Note 5: Defined as the change in positive full scale caused by a 2% variation in the nominal supply voltage. Note 6: It is recommended that RD, WR, and CS are kept high for the quiet time (tQ) and conversion time (tCON). Note 7: Guaranteed by design. Note 1: Note 2: Note 3: Note 4:
Typical Operating Characteristics
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE (MAX1104_)
MAX11044 toc01
DIFFERENTIAL NONLINEARITY vs. CODE (MAX1104_)
0.800 0.600 0.400 INL (LSB) 0.200 0 -0.200 -0.400 -0.600 -0.800 -1.000 0 8192 16384 24576 32768 40960 49152 57344 65536 65536 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25C VRDC = 4.096V
MAX11044 toc02
INL AND DNL vs. ANALOG SUPPLY VOLTAGE (MAX1104_)
MAX11044 toc03
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25C VRDC = 4.096V
1.000
1.0
0.6 INL AND DNL (LSB) MAX DNL MIN INL -0.2
MAX INL VDVDD = 3.3V fSAMPLE = 250ksps TA = +25C VRDC = 4.096V
0.2
-0.6
MIN DNL
-1.0 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
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5
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Typical Operating Characteristics (continued)
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
INL AND DNL vs. TEMPERATURE (MAX1104_)
MAX11044 toc04
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX11046 CONVERTING
MAX11044 toc05
1.5 MAX INL 1.0 INL AND DNL (LSB) 0.5
45
40 MAX11045 CONVERTING IAVDD (mA) 35
0 -0.5 -1.0 -1.5 -40
MIN INL
MAX11046 STATIC
MAX DNL
30 MAX11045 STATIC
VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps VRDC = 4.096V -15 10
TA = +25C, fSAMPLE = 250ksps
MIN DNL
25 MAX11044 CONVERTING 20 MAX11044 STATIC 5.05 5.15 5.25
35
60
85
4.75
4.85
4.95
TEMPERATURE (C)
VAVDD (V)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX11044 toc06
DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE
TA = +25C fSAMPLE = 250ksps MAX11046 CONVERTING
MAX11044 toc07
45
MAX11046 CONVERTING
12 10 8 IDVDD (mA) 6
40 MAX11045 CONVERTING IAVDD (mA) 35 MAX11046 STATIC
30 MAX11045 STATIC 25 MAX11044 CONVERTING 20 -40 -15 10
VAVDD = 5.0V fSAMPLE = 250ksps
MAX11045 CONVERTING 4 MAX11044 CONVERTING 2 MAX11044/MAX11045/MAX11046 STATIC
MAX11044 STATIC 35 60 85 0 2.75 3.25 3.75 4.25 4.75 5.25 VDVDD (V)
TEMPERATURE (C)
6
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX11046 CONVERTING 6.0 4.8 IDVDD (mA) 3.6 2.4 1.2 0 -40 -15 10 35 60 85 TEMPERATURE (C) VDVDD = 3.3V fSAMPLE = 250ksps CDBxx = 15pF MAX11045 CONVERTING
MAX11044 toc08
ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE
VAVDD = 5.0V VDVDD = 3.3V SHUTDOWN CURRENT (A) 4
MAX11044 toc09
ANALOG AND DIGITAL SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
TA = +25C SHUTDOWN CURRENT (A) 4
MAX11044 toc09a
7.2
5
5
3
IAVDD
3
IAVDD
MAX11044 CONVERTING
2 IDVDD 1
2 IDVDD 1
MAX11044/MAX11045/MAX11046 STATIC 0 -40 -15 10 35 60 85 TEMPERATURE (C) 0 2.75 3.25 3.75 4.25 4.75 5.25 VAVDD OR VDVDD (V)
INTERNAL REFERENCE VOLTAGES vs. SUPPLY VOLTAGE
MAX1960 toc10
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
VAVDD = 5.0V 4.108 4.104 UPPER TYPICAL LIMIT
MAX1960 toc11
4.09630 TA = +25C 4.09625 4.09620 VREF (V) VRDC
4.112
4.09610 4.09605 4.09600 4.09595 4.09590 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) VREFIO
VREFIO (V)
4.09615
4.100 4.096 4.092 4.088 4.084 4.080 -40 -15 10 35 60 85 TEMPERATURE (C) LOWER TYPICAL LIMIT
OFFSET ERROR AND OFFSET ERROR MATCHING vs. SUPPLY VOLTAGE
MAX11044 toc12
OFFSET ERROR AND OFFSET ERROR MATCHING vs. TEMPERATURE
fSAMPLE = 250ksps VAVDD = 5.0V VREFIO = 4.096V OFFSET ERROR MATCHING ERRORS (%FS) 0.002
MAX11044 toc13
0.010 fSAMPLE = 250ksps TA = +25C VRDC = 4.096V OFFSET ERROR MATCHING ERRORS (%FS) 0.002
0.010
0.006
0.006
-0.002
OFFSET ERROR
-0.002
OFFSET ERROR
-0.006
-0.006
-0.010 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
-0.010 -40 -15 10 35 60 85 TEMPERATURE (C)
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7
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Typical Operating Characteristics (continued)
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
GAIN ERROR AND GAIN ERROR MATCHING vs. SUPPLY VOLTAGE
MAX11044 toc14
GAIN ERROR AND GAIN ERROR MATCHING vs. TEMPERATURE
MAX11044 toc15
FFT PLOT (MAX1104_)
-20 MAGNITUDE (dB) -40 -60 -80 -100 fIN = 10kHz fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V
MAX11044 toc16
0.010 fSAMPLE = 250ksps TA = +25C VRDC = 4.096V GAIN ERROR ERRORS (%FS) 0.002
0.010 fSAMPLE = 250ksps VAVDD = 5.0V VREFIO = 4.096V GAIN ERROR ERRORS (%FS) 0.002
0
0.006
0.006
-0.002
GAIN ERROR MATCHING
-0.002
GAIN ERROR MATCHING
-0.006
-0.006 -120 -0.010 4.75 4.85 4.95 5.05 5.15 5.25 -40 -15 10 35 60 85 VAVDD (V) TEMPERATURE (C) -140 0 25 50 75 100 125 FREQUENCY (kHz)
-0.010
TWO-TONE IMD PLOT (MAX1104_)
MAX11044 toc17
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE AND DISTORTION RATIO vs. TEMPERATURE (MAX1104_)
fIN = 10kHz fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB FROM FS
MAX11044 toc18
0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 7.2 8.0 8.8 9.6 10.4 11.2 12.0 fIN1 = 9838Hz fIN2 = 10235Hz fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V VRDC = 4.096V VIN = -0.01dBFS
95
94 SNR AND SINAD (dB)
93
SNR
92 SINAD 91
90 12.8 -40 -15 10 35 60 85 FREQUENCY (kHz) TEMPERATURE (C)
TOTAL HARMONIC DISTORTION vs. TEMPERATURE (MAX1104_)
MAX11044 toc19
SNR AND SINAD vs. ANALOG SUPPLY VOLTAGE (MAX1104_)
MAX11044 toc20
-103.5 -104.0 -104.5 THD (dB) -105.0 -105.5 -106.0 -106.5 -40 -15 10 35 60 fIN = 10kHz fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB FROM FS
93.0 SNR SNR AND SINAD (dB) 92.5
92.0 SINAD 91.5 fIN = 10kHz fSAMPLE = 250ksps TA = +25C VRDC = 4.096V VIN = -0.025dB FROM FS 4.75 4.85 4.95 5.05 5.15 5.25
91.0 85 TEMPERATURE (C) VAVDD (V)
8
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
THD vs. ANALOG SUPPLY VOLTAGE (MAX1104_)
fIN = 10kHz fSAMPLE = 250ksps TA = +25C VRDC = 4.096V VIN = -0.025dB FROM FS
MAX11044 toc21
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
SIGNAL-TO-NOISE AND DISTORTION RATIO vs. FREQUENCY (MAX1104_)
MAX11044 toc22
THD vs. INPUT FREQUENCY (MAX1104_)
fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB from FS
MAX11044 toc23
-102
94 92 90 SINAD (dB) 88 86 fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB from FS 0.1 1 10
-85
-103
-90
THD (dB)
THD (dB) 100
-104
-95
-105
-100
-106
84 82 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
-105
-107
-110 0.1 1 10 100 FREQUENCY (kHz) FREQUENCY (kHz)
CROSSTALK vs. FREQUENCY
MAX11044 toc24
OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO AGNDS (MAX1104_)
VCH = 0V VAVDD = 5.0V VRDC = 4.096V fSAMPLE = 250ksps
MAX11044 toc25 MAX11044 toc27
-90 fIN = 60Hz fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB FROM FS INACTIVE CHANNEL AT GND
200,000
NUMBER OF OCCURANCES
-100 CROSSTALK (dB)
150,000
-110
100,000
-120
-130
50,000
-140 0.1 1 10 100 FREQUENCY (kHz)
0 32765 32766 32767 32768 32769 32770 32771
OUTPUT CODE (DECIMAL)
CONVERSION TIME vs. ANALOG SUPPLY VOLATAGE
TA = +25C 2.99 CONVERSION TIME (s) 2.98 2.97 2.96 2.95 2.94 2.93 2.92 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
MAX11044 toc26
CONVERSION TIME vs. TEMPERATURE
3.00 VAVDD = 5.0V 2.99 CONVERSION TIME (s) 2.98 2.97 2.96 2.95 2.94 2.93 2.92 -40 -15 10 35 60 85 TEMPERATURE(C)
3.00
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9
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Pin Description
PIN MAX11044 (TQFN-EP) 1 2 3 4 5 6 7, 21, 50 8, 20, 51 9 10 11 12 13 14 15 16 MAX11045 (TQFN-EP) 1 2 3 4 5 6 7, 21, 50 8, 20, 51 9 10 11 12 13 14 15 16 MAX11046 (TQFN-EP) 1 2 3 4 5 6 7, 21, 50 8, 20, 51 9 10 11 12 13 14 15 16 NAME DB13 DB12 DB11 DB10 DB9 DB8 DGND DVDD DB7 DB6 DB5 DB4 DB3/CR3 DB2/CR2 DB1/CR1 DB0/CR0 FUNCTION 16-Bit Parallel Data Bus Digital Output Bit 13 16-Bit Parallel Data Bus Digital Output Bit 12 16-Bit Parallel Data Bus Digital Output Bit 11 16-Bit Parallel Data Bus Digital Output Bit 10 16-Bit Parallel Data Bus Digital Output Bit 9 16-Bit Parallel Data Bus Digital Output Bit 8 Digital Ground Digital Supply. Bypass to DGND with a 0.1F capacitor at each DVDD input. 16-Bit Parallel Data Bus Digital Output Bit 7 16-Bit Parallel Data Bus Digital Output Bit 6 16-Bit Parallel Data Bus Digital Output Bit 5 16-Bit Parallel Data Bus Digital Output Bit 4 16-Bit Parallel Data Bus Digital Output Bit 3/ Configuration Register Input Bit 3 16-Bit Parallel Data Bus Digital Output Bit 2/ Configuration Register Input Bit 2 16-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit 1 16-Bit Parallel Data Bus Digital Output Bit 0/ Configuration Register Input Bit 0 Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. Convert Start Input. Rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80F total capacitance. See the Layout, Grounding, and Bypassing section. Signal Ground. Connect all AGND and AGNDS inputs together on PWB.
17
17
17
EOC
18
18
18
CONVST
19
19
19
SHDN
22, 28, 35, 43, 49
22, 28, 35, 43, 49
22, 28, 35, 43, 49
RDC
23, 27, 33, 38, 44, 48
23, 27, 33, 38, 44, 48
23, 27, 33, 38, 44, 48
AGNDS
10
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Pin Description (continued)
PIN MAX11044 (TQFN-EP) 24, 30, 41, 47 25, 31, 40, 46 32 34 37 39 36 -- -- -- -- 52 MAX11045 (TQFN-EP) 24, 30, 41, 47 25, 31, 40, 46 29 32 34 37 36 39 42 -- -- 52 MAX11046 (TQFN-EP) 24, 30, 41, 47 25, 31, 40, 46 26 29 32 34 36 37 39 42 45 52 NAME FUNCTION Analog Supply Input. Bypass AVDD to AGND with a 0.1F capacitor at each AVDD input. Analog Ground. Connect all AGND inputs together. Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input External Reference Input/Internal Reference Output. Place a 0.1F capacitor from REFIO to AGND. Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Input Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 16-Bit Parallel Data Bus Digital Output Bit 15 16-Bit Parallel Data Bus Digital Output Bit 14 Internally Connected. Connect to AGND. Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point.
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
AVDD AGND CH0 CH1 CH2 CH3 REFIO CH4 CH5 CH6 CH7 WR
53
53
54
CS
54 55 56 26, 29, 42, 45 --
54 55 56 26, 45 --
54 55 56 -- --
RD DB15 DB14 I.C. EP
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11
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Pin Description (continued)
PIN MAX11044 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 MAX11045 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 MAX11046 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 NAME DB14 DB13 DB12 DB11 DB10 DB9 DB8 DGND DVDD DB7 DB6 DB5 DB4 DB3/CR3 DB2/CR2 DB1/CR1 DB0/CR0 FUNCTION 16-Bit Parallel Data Bus Digital Output Bit 14 16-Bit Parallel Data Bus Digital Output Bit 13 16-Bit Parallel Data Bus Digital Output Bit 12 16-Bit Parallel Data Bus Digital Output Bit 11 16-Bit Parallel Data Bus Digital Output Bit 10 16-Bit Parallel Data Bus Digital Output Bit 9 16-Bit Parallel Data Bus Digital Output Bit 8 Digital Ground Digital Supply. Bypass to DGND with a 0.1F capacitor at each DVDD input. 16-Bit Parallel Data Bus Digital Output Bit 7 16-Bit Parallel Data Bus Digital Output Bit 6 16-Bit Parallel Data Bus Digital Output Bit 5 16-Bit Parallel Data Bus Digital Output Bit 4 16-Bit Parallel Data Bus Digital Output Bit 3/ Configuration Register Input Bit 3 16-Bit Parallel Data Bus Digital Output Bit 2/ Configuration Register Input Bit 2 16-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit 1 16-Bit Parallel Data Bus Digital Output Bit 0/ Configuration Register Input Bit 0 Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. Convert Start Input. Rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. Signal Ground. Connect all AGND and AGNDS inputs together on PWB. Analog Supply Input. Bypass AVDD to AGND with a 0.1F capacitor at each AVDD input. Analog Ground. Connect all AGND inputs together.
18
18
18
EOC
19
19
19
CONVST
20
20
20
SHDN
23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56
23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56
23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56
AGNDS AVDD AGND
12
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Pin Description (continued)
PIN MAX11044 (TQFP-EP) 26, 55 27, 33, 40, 48, 54 37 39 42 44 41 -- -- -- -- 61 MAX11045 (TQFP-EP) 26, 55 27, 33, 40, 48, 54 34 37 39 42 41 44 47 -- -- 61 MAX11046 (TQFP-EP) 26, 55 27, 33, 40, 48, 54 31 34 37 39 41 42 44 47 50 61 NAME RDC_SENSE FUNCTION Reference Buffer Sense Feedback. Connect to RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80F total capacitance. See the Layout, Grounding, and Bypassing section. Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input External Reference Input/Internal Reference Output. Place a 0.1F capacitor from REFIO to AGND. Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Input Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 16-Bit Parallel Data Bus Digital Output Bit 15 Internally Connected. Connect to AGND. Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point.
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
RDC
CH0 CH1 CH2 CH3 REFIO CH4 CH5 CH6 CH7 WR
62
62
62
CS
63 64 31, 34, 47, 50 --
63 64 31, 50 --
63 64 -- --
RD DB15 I.C. EP
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13
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Pin Description (continued)
PIN MAX11054 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 18 MAX11055 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 18 MAX11056 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 18 NAME DB12 DB11 DB10 DB9 DB8 DB7 DB6 DGND DVDD DB5 DB4 DB3 DB2 DB1/CR3 DB0/CR2 CR1 CR0 EOC FUNCTION 14-Bit Parallel Data Bus Digital Output Bit 12 14-Bit Parallel Data Bus Digital Output Bit 11 14-Bit Parallel Data Bus Digital Output Bit 10 14-Bit Parallel Data Bus Digital Output Bit 9 14-Bit Parallel Data Bus Digital Output Bit 8 14-Bit Parallel Data Bus Digital Output Bit 7 14-Bit Parallel Data Bus Digital Output Bit 6 Digital Ground Digital Supply. Bypass to DGND with a 0.1F capacitor at each DVDD input. 14-Bit Parallel Data Bus Digital Output Bit 5 14-Bit Parallel Data Bus Digital Output Bit 4 14-Bit Parallel Data Bus Digital Output Bit 3 14-Bit Parallel Data Bus Digital Output Bit 2 14-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit 3 14-Bit Parallel Data Bus Digital Output Bit 0/ Configuration Register Input Bit 2 Configuration Register Input Bit 1 Configuration Register Input Bit 0 Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. Convert Start Input. Rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. Signal Ground. Connect all AGND and AGNDS inputs together on PWB. Analog Supply Input. Bypass AVDD to AGND with a 0.1F capacitor at each AVDD input. Analog Ground. Connect all AGND inputs together. Reference Buffer Sense Feedback. Connect to RDC plane.
19
19
19
CONVST
22, 28, 35, 43, 49 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55
22, 28, 35, 43, 49 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55
22, 28, 35, 43, 49 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55
SHDN
AGNDS AVDD AGND RDC_SENSE
14
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Pin Description (continued)
PIN MAX11054 (TQFP-EP) 27, 33, 40, 48, 54 37 39 42 44 41 -- -- -- -- 61 MAX11055 (TQFP-EP) 27, 33, 40, 48, 54 34 37 39 42 41 44 47 -- -- 61 MAX11056 (TQFP-EP) 27, 33, 40, 48, 54 31 34 37 39 41 42 44 47 50 61 NAME FUNCTION
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
RDC
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80F total capacitance. See the Layout, Grounding, and Bypassing section. Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input External Reference Input/Internal Reference Output. Place a 0.1F capacitor from REFIO to AGND. Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Input Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 14-Bit Parallel Data Bus Digital Output Bit 14 Internally Connected. Connect to AGND. Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point.
CH0 CH1 CH2 CH3 REFIO CH4 CH5 CH6 CH7 WR
62
62
62
CS
63 64 31, 34, 47, 50 --
63 64 31, 50 --
63 64 -- --
RD DB13 I.C. EP
Detailed Description
The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 are fast, low-power ADCs that combine 4, 6, or 8 independent ADC channels in a single IC. Each channel includes simultaneously sampling independent T/H circuitry that preserves relative phase information between inputs making the MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056 ideal for motor control and power monitoring. The MAX11044/MAX11045/MAX11046 and MAX11054/MAX11055/MAX11056 are available with 5V input ranges that feature 20mA overrange, faulttolerant inputs. The MAX11044/MAX11045/MAX11046
and MAX11054/MAX11055/MAX11056 operate with a single 4.75V to 5.25V supply. A separate 2.7V to 5.25V supply for digital circuitry makes the devices compatible with low-voltage processors. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 perform conversions for all channels in parallel by activating independent ADCs. Results are available through a high-speed, 20MHz, parallel data bus after a conversion time of 3s following the end of a sample. The data bus is bidirectional and allows for easy programming of the configuration register. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 feature a reference buffer, which
15
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
is driven by an internal bandgap reference circuit (VREFIO = 4.096V). Drive REFIO with an external reference or bypass with 0.1F capacitor to ground when using the internal reference. When in external reference mode, drive VREFIO with a 3.0V to 4.25V source, resulting in an input range of 3.662V to 5.188V, respectively. All analog inputs are fault-protected to up to 20mA. The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 include an input clamping circuit that activates when the input voltage at the analog input is above (VAVDD + 300mV) or below -(VAVDD + 300mV). The clamp circuit remains high impedance while the input signal is within the range of VAVDD and draws little or almost no current. However, when the input signal exceeds V AVDD , the clamps begin to turn on and shunt current to/from the AVDD supply. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed (VAVDD + 0.3V). To make use of the input clamps (see Figure 1), connect a resistor (RS) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the MAX11044/MAX11045/ MAX11046 and MAX11054/MAX11055/MAX11056 does not exceed 20mA. Note that the voltage at the analog input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS:
Analog Inputs
Track and Hold (T/H) To preserve phase information across all channels, each input includes a dedicated T/H circuitry. The input tracking circuitry provides a 4MHz small-signal bandwidth, enabling the device to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Input Range and Protection The full-scale analog input voltage is a product of the reference voltage. For the MAX11044/MAX11045/ MAX11046 and MAX11054/MAX11055/MAX11056, the full-scale input is bipolar in the range of:
(VREFIO x 5 ) 4.096
PIN VOLTAGE INPUT SIGNAL RS AVDD
DVDD DB15**
8 x 16-/14-BIT REGISTERS
SOURCE
BIDIRECTIONAL DRIVERS
CH0
CLAMP
S/H
16-/14-BIT ADC
DB4 DB3/CR3 DB0/CR0
CH7
CLAMP
S/H
16-/14-BIT ADC
AGNDS
CONFIGURATION REGISTERS INTERFACE AND CONTROL
WR RD CS CONVST SHDN EOC DGND RDC RDC_SENSE*
AGND MAX11044/MAX11045/MAX11046/ MAX11054/MAX11055/MAX11056 INT REF 10k BANDGAP REFERENCE REFIO EXT REF
REF BUF
*CONNECTED INTERNALLY ON THE TQFN PARTS TO RDC **MAX11044/MAX11045/MAX11046 MAX11046/MAX11056
Figure 1. Required Setup for Clamp Circuit
16 ______________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
RS = VFAULT _ MAX - 7V 20mA
where VFAULT_MAX is the maximum voltage that the source produces during a fault condition. Figures 2 and 3 illustrate the clamp circuit voltage-current characteristics for a source impedance R S = 1280. While the input voltage is within the (VAVDD + 300mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin.
CR2 (Output Data Format) CR2 selects the output data format. The POR default = 0. 0 = offset binary. 1 = two's complement. CR1 (Reserved)
CR1 must be set to 0.
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Applications Information
Digital Interface
The bidirectional, parallel, digital interface, CR0-CR3, sets the 4-bit configuration register. This interface configures the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), and convert start (CONVST). Figures 6 and 7 and the Timing Characteristics in the Electrical Characteristics table show the operation of the interface. DB0-DB15/DB13 output the 16-/14-bit conversion result. All bits are high impedance when RD = 1 or CS = 1.
CR0 (CONVST Mode) CR0 selects the acquisition mode. The POR default = 0. 0 = CONVST controls the acquisition and conversion. Drive CONVST low to start acquisition. The rising edge of CONVST begins the conversion. 1 = acquisition mode starts as soon as the previous conversion is complete. The rising edge of CONVST begins the conversion. Programming the Configuration Register To program the configuration register, bring the CS and WR low and apply the required configuration data on CR3-CR0 of the bus and then raise WR once to save changes.
CAUTION: When the configuration register is not being programmed, the host driving CR3-CR0 must relinquish the bus when the conversion results of the ADC are being read!
CR3 (Int/Ext Reference) CR3 selects the internal or external reference. The POR default = 0. 0 = internal reference, REFIO internally driven through a 10k resistor, bypass with 0.1F capacitor to AGND. 1 = external reference, drive REFIO with a high-quality reference.
Table 1. Configuration Register
CR3 Int/Ext Reference CR2 Output Data Format CR1 Must be set to 0 CR0 CONVST Mode
MAX11044 fig02
20 10 0 -10 -20 -30
RS = 1280 VAVDD = 5V AT CH_ INPUT
20 10
RS = 1280 VAVDD = 5V AT CH_ INPUT
ICLAMP (mA)
ICLAMP (mA)
AT SOURCE 0 -10 -20 -30
AT SOURCE
-50
-30
-10
10
30
50
-8
-6
-4
-2
0
2
4
6
8
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
Figure 2. Input Clamp Characteristics
Figure 3. Input Clamp Characteristics (Zoom In)
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MAX11044 fig03
30
30
17
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Starting a Conversion
CONVST initiates conversions. The MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056 provide two acquisition modes set through the configuration register. Allow a quiet time (tQ) of 500ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample. In default mode (CR0 = 0), drive CONVST low to place the MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 into acquisition mode. All the input switches are closed and the internal T/H circuits track the respective input voltage. Keep the CONVST signal low for at least 1s (tACQ) to enable proper settling of the sampled voltages. On the rising edge of CONVST, the switches are opened and the MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 begin the conversion on all the samples in parallel. EOC remains high until the conversion is completed. In the second mode (CR0 = 1), the MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056 enter acquisition mode as soon as the previous conversion is completed. CONVST rising edge initiates the next sample and conversion sequence. CONVST needs to be low for at least 20ns to be valid. Provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056.
Reading Conversion Results
The CS and RD are active-low, digital inputs that control the readout through the 16-/14-bit, parallel, 20MHz data bus (D0-D15/D13). After EOC transitions low, read the conversion data by driving CS and RD low. Each low period of RD presents the next channel's result. When CS or RD are high, the data bus is high impedance. CS may be driven high between individual channel readouts or left low during the entire 8-channel readout.
Reference
Internal Reference The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 feature a precision, low-drift, internal bandgap reference. Bypass REFIO with a 0.1F capacitor to AGND to reduce noise. The REFIO output voltage may be used as a reference for other circuits. The output impedance of REFIO is 10k. Drive only high impedance circuits or buffer externally when using REFIO to drive external circuitry. External Reference Set the configuration register to disable the internal reference and drive REFIO with a high-quality external reference. To avoid signal degradation, ensure that the integrated reference noise applied to REFIO is less than 10V in the bandwidth of up to 50kHz.
CS (USER SUPPLIED) t5 t3 WR (USER SUPPLIED) t7 t6 CONFIGURATION REGISTER t4
CS (USER SUPPLIED) t8 RD (USER SUPPLIED) t12 Sn t13 t9 t10 t11
DB0-DB15
Sn + 1
CR0-CR3 (USER SUPPLIED)
Figure 4. Programming Configuration-Register Timing Requirements
Figure 5. Readout Timing Requirements
18
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
SAMPLE
tCON CONVST
tACQ
t1 EOC
tO
tQ
CS
RD
DB0-DB15 S0 S1 S6 S7
Figure 6. Conversion Timing Diagram (CR0 = 0)
SAMPLE
tCON CONVST
tACQ
t2 EOC
tO
tQ
CS
RD
DB0-DB15 S0 S1 S6 S7
Figure 7. Conversion Timing Diagram (CR0 = 1)
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Reference Buffer The MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056 have a built-in reference buffer to provide a low-impedance reference source to the SAR converters. This buffer is used in both internal and external reference mode. The reference buffer output feeds five RDC pins. The RDC pins should be all connected together on the PCB. The reference buffer is
VLSB = (10/4.096) x (VREF/65,536) 7FFF 7FFE OUTPUT CODE (hex) OUTPUT CODE (hex) -FS = -32,768 x VLSB 0001 0000 FFFF FFFE V OUTPUT CODE = IN + 32,768 VLSB +FS = 32,767 x VLSB FULL-SCALE TRANSITION FFFF FFFE -FS = -32,768 x VLSB VIN OUTPUT CODE = VLSB
externally compensated and requires at least 10F on the RDC node. For best performance, provide a total of at least 80F on the RDC outputs.
Transfer Functions
Figures 8 and 9 show the transfer functions for all the formats and devices. Code transitions occur halfway between successive-integer LSB values.
VLSB = (10/4.096) x (VREF/65,536) +FS = 32,767 x VLSB FULL-SCALE TRANSITION
8001 8000 7FFF 7FFE
8001 8000 -FS 0 +32,766.5 x VLSB INPUT VOLTAGE (LSB) +FS
0001 0000 -FS 0 -32,767.5 x VLSB +32,766.5 x VLSB INPUT VOLTAGE (LSB) +FS
-32,767.5 x VLSB
Figure 8. Two's Complement Transfer Function for 16-Bit Devices
VLSB = (10/4.096) x (VREF/16,384) 1FFF 1FFE OUTPUT CODE (hex) -FS = -8192 x VLSB 0001 0000 3FFF 3FFE OUTPUT CODE = VIN + 8192 VLSB +FS = 8191 x VLSB FULL-SCALE TRANSITION
Figure 9. Offset-Binary Transfer Function for 16-Bit Devices
VLSB = (10/4.096) x (VREF/16,384) 3FFF 3FFE OUTPUT CODE (hex) -FS = -8192 x VLSB V OUTPUT CODE = IN VLSB +FS = 8191 x VLSB FULL-SCALE TRANSITION
2001 2000 1FFF 1FFE
2001 2000 -FS -8191.5 x VLSB 0 +8190.5 x VLSB INPUT VOLTAGE (LSB) +FS
0001 0000 -FS 0 -8191.5 x VLSB +8190.5 x VLSB INPUT VOLTAGE (LSB) +FS
Figure 8b. Two's Complement Transfer Function for 14-Bit Devices
Figure 9b. Offset-Binary Transfer Function for 14-Bit Devices
20
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
VOLTAGE TRANSFORMER OPT
PHASE 1
ADC OPT CURRENT TRANSFORMER VN ADC
ADC
NEUTRAL
IN
ADC
LOAD 1
MAX11046/ MAX11056
LOAD 3 I3 ADC
LOAD 2
V3 I2 PHASE 2 V2
ADC
ADC
ADC PHASE 3
Figure 10. Power-Grid Protection
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21
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
DSP-BASED DIGITAL PROCESSING ENGINE
MAX11044/ MAX11045/ MAX11046/ MAX11054/ MAX11055/ MAX11056
16-/14-BIT ADC 16-/14-BIT ADC 16-/14-BIT ADC 16-/14-BIT ADC 16-/14-BIT ADC IPHASE1
IGBT CURRENT DRIVERS
IPHASE3 IPHASE2
3-PHASE ELECTRIC MOTOR
POSITION ENCODER
Figure 11. DSP Motor Control
22
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Layout, Grounding, and Bypassing
For best performance use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect DGND, AGND, and AGNDS pins on the MAX11044/MAX11045/MAX11046 and MAX11054/MAX11055/MAX11056 to this ground plane. Keep the ground return to the power supply for this ground low impedance and as short as possible for noisefree operation. To achieve the highest performance, connect all the RDC pins (22, 28, 35, 43, 49 for the TQFN package, or pins 27, 33, 40, 48, 54 for the TQFP package) to a local RDC plane on the PCB. In addition, on the TQFP package, the RDC_SENSE pins 26 and 55 should be directly connected to this RDC plane as well. Bypass the RDC outputs with a total of at least 80F of capacitance. If two capacitors are used, place each as close as possible to pins 22 and 49 (TQFN) or pins 27 and 54 (TQFP). If four capacitors are used, place each as close as possible to pins 22, 28, 43, and 49 (TQFN) or pins 27, 33, 48, and 54 (TQFP). For example, two 47F, 10V X5R capacitors in 1210 case size can be placed as close as possible to pins 22 and 49 (TQFN package) will provide excellent performance. Alternatively, four 22F, 10V X5R capacitors in 1210 case size placed as close as possible to pins 22, 28, 43, and 49 (TQFN package) will also provide good performance. Ensure that each capacitor is connected directly into the GND plane with an independent via. If Y5U or Z5U ceramics are used, be aware of the highvoltage coefficient these capacitors exhibit and select higher voltage rating capacitors to ensure that at least 80F of capacitance is on the RDC plane when the plane is driven to 4.096V by the built-in reference buffer. For example, a 22F X5R with a 10V rating is approximately 20F at 4.096V, whereas, the same capacitor in Y5U ceramic is just 13F. However, a Y5U 22F capacitor with a 25V rating cap is approximately 20F at 4.096V. Bypass AVDD and DVDD to the ground plane with 0.1F ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10F decoupling capacitor to AVDD and DVDD per PCB. Interconnect all of the AVDD inputs and DVDD inputs using two solid power planes. For best performance, bring the AVDD power plane in on the analog interface side of the MAX11044/ MAX11045/MAX11046 and MAX11054/MAX11055/ MAX11056 and the DVDD power plane from the digital interface side of the device. For acquisition periods near minimum (1s) use a 1nF C0G ceramic chip capacitor between each of the channel inputs to the ground plane as close as possible to the MAX11044/MAX11045/MAX11046 and MAX11054/ MAX11055/MAX11056. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit.
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Typical Application Circuits
Power-Grid Protection Figure 10 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application.
Definitions
Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function. For example, -0.9 LSB guarantees no missing code while -1.1 LSB results in missing code. Offset Error The offset error is defined as the input voltage required to cause the MAX11044/MAX11045/MAX11046 digital output to be centered on code 0X8000 (offset binary) or 0x0000 (two's complement) and the MAX11054/ MAX11055/MAX11056 digital output to be centered on code 0X2000 (offset binary) or 0x0000 (two's complement). Ideally, this input voltage should be 0V with respect to GND. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (10/4.096) x V REF x (65,534/65,536) for 16-bit, or (10/4.096) x VREF x (16,382/16,384) for 14-bit devices. For the MAX11044/MAX11045/MAX11046, top code tran23
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
sition is 0x7FFE to 0x7FFF in two's complement mode and 0xFFFE to 0xFFFF in offset binary mode. The bottom code transition is 0x8000 and 0x8001 in two's complement mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11054/MAX11055/MAX11056, top code transition is 0x1FFE to 0x1FFF in two's complement mode and 0x3FFE to 0x3FFF in offset binary mode. The bottom code transition is 0x2000 and 0x2001 in two's complement mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11044/MAX11045/MAX11046 and MAX11054/MAX11055/MAX11056, the analog input voltage to produce these code transitions is measured and the gain error is computed by subtracting (10/4.096) x V REF x (65,534/65,536) or (10/4.096) x V REF x (16,382/16,384), respectively from this measurement.
Total Harmonic Distortion (THD) THD is the ratio of the RMS of the first five harmonics of the input signal to the fundamental itself. This is: expressed as: V22 + V32 + V42 + V52 THD = 20 x log V1
where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in aperture delay. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the other channels. Channel-to-channel isolation is measured by applying DC to channels 1 to 7, while a -0.4dBFS sine wave at 60Hz is applied to channel 0. A 10ksps FFT is taken for channel 0 and channel 1. Channel-to-channel isolation is expressed in dB as the power ratio of the two 60Hz magnitudes. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal's slew rate does not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as fullpower input bandwidth frequency.
Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC's resolution (N bits): SNR = (6.02 x N + 1.76)dB
where N = 16/14 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals:
SignalRMS SINAD(dB) = 10 x log (Noise + Distortion)RMS
Effective Number of Bits (ENOB) The ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows:
ENOB = SINAD - 1.76 6.02
24
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Positive Full-Scale Error The error in the input voltage that causes the last code transition of FFFE to FFFF (hex) for 16-bit or 3FFE to 3FFF (hex) for 14-bit devices (in default offset binary mode) or 7FFE to 7FFF (hex) for 16-bit or 1FFE to 1FFF (hex) for 14bit devices (in two's complement mode) from the ideal input voltage of 32,766.5 x (10/4.096) x (VREF/65,536) for 16-bit or 8190.5 x (10/4.096) x (VREF/16,384) for 14-bit devices after correction for offset error. Negative Full-Scale Error The error in the input voltage that causes the first code transition of 0000 to 0001 (hex) (in default offset binary mode) or 8000 to 8001 (hex) for 16-bit or 2000 to 2001 (hex) for 14-bit devices (in two's complement mode) from the ideal input voltage of -32,767.5 x (10/4.096) x (V REF /65,536) for 16-bit or -8191.5 x (10/4.096) x (VREF/16,384) for 14-bit devices after correction for offset error.
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Chip Information
PROCESS: BiCMOS
Pin Configurations
CH5*/CH4/CH3 CH4*/CH3/CH2 CH3*/CH2/CH1 CH6*/CH5/I.C. CH2*/CH1/CH0 CH1*/CH0/I.C.
AGNDS
CH5*/CH4/CH3
CH4*/CH3/CH2
CH3*/CH2/CH1
CH2*/CH1/CH0
CH6*/CH5/I.C.
CH1*/CH0/I.C.
AGNDS
AGND
AGND
REFIO
AVDD
AVDD
RDC
RDC
AGNDS
AGND
REFIO
AGND
AVDD
RDC
AVDD
TOP VIEW
AGNDS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 AGNDS 31 CH0*/I.C. 30 AGND 29 AVDD 28 AGNDS 27 RDC 26 RDC_SENSE
42 41 40 39 38 37 36 35 34 33 32 31 30 29 RDC 43 AGNDS 44 I.C./CH7* 45 28 RDC 27 AGNDS 26 CH0*/I.C.
AGNDS 49 I.C./CH7* 50 AGND 51 AVDD 52 AGNDS 53 RDC 54 RDC_SENSE 55 AGND 56 AVDD 57 AGNDS 58 DGND 59 DVDD 60 WR 61 CS 62 RD 63 DB15 64 *EP
AGND 46 AVDD 47 AGNDS 48 RDC 49 DGND 50 DVDD 51 WR 52 CS 53 RD 54 DB15 55 DB14 56 1 DB13 2 DB12 3 DB11 4 DB10 5 DB9 6 DB8 7 DGND 8 DVDD 9 DB7 10 11 12 13 14 DB6 DB5 DB4 CR3/DB3 CR2/DB2 *EP
25 AGND 24 AVDD 23 AGNDS
MAX11044 MAX11045 MAX11046
22 RDC 21 DGND 20 DVDD 19 SHDN 18 CONVST 17 EOC
MAX11044 MAX11045 MAX11046
RDC
25 AGND 24 AVDD 23 AGNDS 22 DGND 21 DVDD 20 SHDN 19 CONVST
+
16 DB0/CR0 15 DB1/CR1
+
18 EOC 17 DB0/CR0
1 DB14
2 DB13
3 DB12
4 DB11
5 DB10
6 DB9
7 DB8
8 DGND
9 DVDD
10 11 12 13 14 15 16 DB7 DB6 DB5 DB4 CR3/DB3 CR2/DB2 CR1/DB1
TQFN 8mm x 8mm
MAX11044 MAX11045
*MAX11046
TQFP 10mm x 10mm
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25
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
Pin Configurations (continued)
CH5*/CH4/CH3 CH4*/CH3/CH2 CH3*/CH2/CH1 CH2*/CH1/CH0 CH6*/CH5/I.C. CH1*/CH0/I.C.
AGNDS
AGNDS
AGND
AGND
REFIO
AVDD
AVDD
RDC
RDC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 AGNDS 31 CH0*/I.C. 30 AGND 29 AVDD 28 AGNDS 27 RDC 26 RDC_SENSE
AGNDS 49 I.C./CH7* 50 AGND 51 AVDD 52 AGNDS 53 RDC 54 RDC_SENSE 55 AGND 56 AVDD 57 AGNDS 58 DGND 59 DVDD 60 WR 61 CS 62 RD 63 DB13 64 *EP
MAX11054 MAX11055 MAX11056
RDC
25 AGND 24 AVDD 23 AGNDS 22 DGND 21 DVDD 20 SHDN 19 CONVST
+
18 EOC 17 CR0
1 DB12
2 DB11
3 DB10
4 DB9
5 DB8
6 DB7
7 DB6
8 DGND
9 DVDD
10 11 12 13 14 15 16 DB5 DB4 DB3 DB2 CR3/DB1 CR2/DB0 CR1
MAX11054 MAX11055
TQFP 10mm x 10mm
*MAX11056
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 56 TQFN-EP 64 TQFP-EP PACKAGE CODE T5688+3 C64E+6 OUTLINE NO. 21-0135 21-0084 LAND PATTERN NO. 90-0047 90-0328
26
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Revision History
REVISION NUMBER 0 1 2 3 REVISION DATE 10/09 3/10 5/10 9/10 Initial release Added TQFP package to data sheet Added 14-bit MAX11054/MAX11055/MAX11056 Style edits, specified part numbers in Typical Operating Characteristics, corrected pin names, clarified layout Released the TQFP versions of MAX11044, MAX11045, and MAX11046. Revised the Electrical Characteristics, Typical Operating Characteristics, and the Input Range and Protection section. Released MAX11054, MAX11055, MAX11056. Revised the Electrical Characteristics and Figures 8b and 9b. DESCRIPTION PAGES CHANGED -- 1, 2, 8, 9, 19 1-4, 7, 9-26 1, 3-8, 13-18, 22 1-8, 15
MAX11044/MAX11045/MAX11046/MAX11054/MAX11055/MAX11056
4
10/10
5
1/11
1, 2, 4, 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
(c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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